ql3025 / ql3025r 25,000 usable pld gate pasic ? 3 fpga combining high performance and high density 2-27 high performance and high density -25,000 usable pld gates with 204 i/os -16-bit counter speeds over 250 mhz, data path speeds over 275 mhz -0.35 m m four-layer metal non-volatile cmos process for smallest die sizes easy to use / fast development cycles -100% routable with 100% utilization and complete pin-out stability -variable-grain logic cells provide high performance and 100% utilization -comprehensive design tools include high quality verilog/vhdl synthesis high speed embedded sram available in ?r? versions -14 dual-port ram modules, organized in user-configurable 1,152-bit blocks -5ns access times, each port independently accessible -fast and efficient for fifo, ram, and rom functions advanced i/o capabilities -interfaces with both 3.3 volt and 5.0 volt devices -pci compliant with 3.3v and 5.0v buses for -1/-2/-3/-4 speed grades -full jtag boundary scan -registered i/o cells with individually controlled clocks and output enables ? 25,000 usable pld gates, 204 i/o pins 672 logic cells pasic 3 2 ql3025 block diagram preliminary data march, 1998 pasic 3 highlights 16,128 bit ram option ql3025-rev. a
ql3025 / ql3025r 2- 28 the ql3025 is a 25,000 usable pld gate member of the pasic 3 family of fpgas. pasic 3 fpgas are fabricated on a 0.35 m m four-layer metal process using quicklogic?s patented vialink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of- use. the ql3025 contains 672 logic cells. with a maximum of 204 i/os, the ql3025 is available in 144-pin tqfp, 208-pqfp, and 256-pin pbga packages. the ql3025r also includes 14 dual port ram modules, each with 1,152 bits, for a total of 16,128 ram bits. software support for the complete pasic 3 family, including the ql3025, is available through three basic packages. the turnkey quick works package provides the most complete fpga software solution from design entry to logic synthesis, to place and route, to simulation. the quick chip tm and quick tools tm packages provide a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, viewlogic, veribest, or other third- party tools for design entry, synthesis, or simulation. total of 204 i/o pins - 196 bidirectional input/output pins, pci-comp liant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades - 4 high-drive input-only pins - 4 high-drive input/distributed network pins four low-skew distributed networks - two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin - two global clock/control networks available to the logic cell f1, clock, set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance - input + logic cell + output total delays under 6 ns - data path speeds exceeding 275 mhz - counter speeds over 250 mhz product summary features ql3025-rev. a
ql3025 / ql3025r 2- 29 pinout diagrams 144-pin tqfp ql3025-1pf144c pasic 208-pin pqfp ql3025-1pq208c pasic pasic 3 2 pin # 1 pin # 1 pin # 109 pin # 157 pin # 37 pin # 105 pin # 73 pin # 53 ql3025-rev. a
ql3025 / ql3025r 2- 30 pqfp 208 and tqfp 144 pinout table 208 144 function 208 144 function 208 144 function 208 144 function 208 144 function pqfp tqfp pqfp tqfp pqfp tqfp pqfp tqfp pqfp tqfp 1 nc i/o 43 30 gnd 85 60 i/o 127 87 gnd 169 117 i/o 2 1 i/o 44 31 i/o 86 61 i/o 128 88 i/o 170 118 i/o 3 2 i/o 45 nc i/o 87 nc i/o 129 89 i 171 119 i/o 4 3 i/o 46 32 i/o 88 62 i/o 130 90 aclk / i 172 120 i/o 5 nc i/o 47 nc i/o 89 63 i/o 131 91 vcc 173 nc i/o 6 4 i/o 48 33 i/o 90 nc i/o 132 92 i 174 nc i/o 7 5 i/o 49 nc i/o 91 nc i/o 133 93 gclk / i 175 121 i/o 8 nc i/o 50 34 i/o 92 64 i/o 134 94 vcc 176 nc i/o 9 6 i/o 51 35 i/o 93 nc i/o 135 95 i/o 177 122 gnd 10 7 vcc 52 36 i/o 94 65 i/o 136 nc i/o 178 123 i/o 11 nc i/o 53 37 i/o 95 66 gnd 137 96 i/o 179 124 i/o 12 nc gnd 54 38 tdi 96 67 i/o 138 nc i/o 180 nc i/o 13 8 i/o 55 39 i/o 97 nc vcc 139 97 i/o 181 125 i/o 14 nc i/o 56 nc i/o 98 nc i/o 140 98 i/o 182 126 gnd 15 9 i/o 57 40 i/o 99 68 i/o 141 nc i/o 183 127 i/o 16 nc i/o 58 nc i/o 100 69 i/o 142 99 i/o 184 128 i/o 17 10 i/o 59 nc gnd 101 nc i/o 143 nc i/o 185 129 i/o 18 11 i/o 60 41 i/o 102 70 i/o 144 100 i/o 186 nc i/o 19 12 i/o 61 42 vcc 103 71 trstb 145 nc vcc 187 130 vccio 20 13 i/o 62 43 i/o 104 72 tms 146 101 i/o 188 131 i/o 21 nc i/o 63 nc i/o 105 nc i/o 147 102 gnd 189 132 i/o 22 14 i/o 64 44 i/o 106 73 i/o 148 103 i/o 190 nc i/o 23 15 gnd 65 45 i/o 107 nc i/o 149 104 i/o 191 133 i/o 24 16 i/o 66 nc i/o 108 74 i/o 150 nc i/o 192 134 i/o 25 17 i 67 46 i/o 109 75 i/o 151 105 i/o 193 nc i/o 26 18 aclk / i 68 47 i/o 110 76 i/o 152 106 i/o 194 135 i/o 27 19 vcc 69 48 i/o 111 77 i/o 153 nc i/o 195 136 i/o 28 20 i 70 nc i/o 112 nc i/o 154 107 i/o 196 nc i/o 29 21 gclk / i 71 49 i/o 113 78 i/o 155 nc i/o 197 137 i/o 30 22 vcc 72 nc i/o 114 79 vcc 156 108 i/o 198 nc i/o 31 23 i/o 73 50 gnd 115 80 i/o 157 109 tck 199 138 gnd 32 nc i/o 74 51 i/o 116 nc gnd 158 110 stm 200 139 i/o 33 24 i/o 75 52 i/o 117 81 i/o 159 111 i/o 201 nc vcc 34 nc i/o 76 nc i/o 118 82 i/o 160 nc i/o 202 140 i/o 35 25 i/o 77 53 i/o 119 nc i/o 161 112 i/o 203 nc i/o 36 nc i/o 78 54 gnd 120 83 i/o 162 113 i/o 204 141 i/o 37 26 i/o 79 55 i/o 121 nc i/o 163 nc gnd 205 142 i/o 38 27 i/o 80 56 i/o 122 84 i/o 164 nc i/o 206 nc i/o 39 28 i/o 81 nc i/o 123 85 i/o 165 114 vcc 207 143 tdo 40 nc i/o 82 57 i/o 124 nc i/o 166 115 i/o 208 144 i/o 41 nc vcc 83 58 vccio 125 86 i/o 167 116 i/o 42 29 i/o 84 59 i/o 126 nc i/o 168 nc i/o ql3025-rev. a
ql3025 / ql3025r 2- 31 pinout diagram 256-pin pbga top bottom ql3025-1pb256c pasic pasic 3 2 a b c d e f g h j k l m n p r t u v w y 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 pin a1 corner ql3025-rev. a
ql3025 / ql3025r 2- 32 pbga 256 pinout table 256 function 256 function 256 function 256 function 256 function 256 function pbga pbga pbga pbga pbga pbga a1 vss c4 i/o e19 i/o l2 aclk / i t17 i/o v20 i/o a2 i/o c5 i/o e20 i/o l3 i t18 i/o w1 i/o a3 i/o c6 i/o f1 i/o l4 gclk / i t19 nc w2 i/o a4 i/o c7 i/o f2 i/o l17 vcc t20 i/o w3 tdi a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 i/o a6 i/o c9 vccio f4 vcc l19 i/o u2 i/o w5 i/o a7 i/o c10 i/o f17 vcc l20 i/o u3 i/o w6 i/o a8 i/o c11 i/o f18 nc m1 i/o u4 vss w7 i/o a9 i/o c12 i/o f19 i/o m2 i/o u5 i/o w8 i/o a10 i/o c13 i/o f20 i/o m3 i/o u6 vcc w9 i/o a11 i/o c14 i/o g1 i/o m4 nc u7 i/o w10 i/o a12 i/o c15 i/o g2 nc m17 nc u8 vss w11 i/o a13 i/o c16 i/o g3 i/o m18 i/o u9 i/o w12 i/o a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 i/o a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 i/o a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 i/o a17 i/o c20 i/o g19 nc n2 i/o u13 vss w16 i/o a18 i/o d1 i/o g20 i/o n3 i/o u14 i/o w17 i/o a19 tck d2 i/o h1 i/o n4 vss u15 vcc w18 i/o a20 i/o d3 i/o h2 i/o n17 vss u16 i/o w19 i/o b1 tdo d4 vss h3 i/o n18 i/o u17 vss w20 trstb b2 i/o d5 i/o h4 vss n19 i/o u18 i/o y1 i/o b3 i/o d6 vcc h17 vss n20 i/o u19 i/o y2 nc b4 i/o d7 i/o h18 i/o p1 i/o u20 i/o y3 i/o b5 i/o d8 vss h19 i/o p2 i/o v1 i/o y4 i/o b6 i/o d9 i/o h20 i/o p3 i/o v2 nc y5 i/o b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 i/o b8 i/o d11 vcc j2 i/o p17 i/o v4 i/o y7 i/o b9 i/o d12 i/o j3 nc p18 i/o v5 i/o y8 i/o b10 i/o d13 vss j4 i/o p19 nc v6 i/o y9 i/o b11 i/o d14 i/o j17 nc p20 i/o v7 i/o y10 i/o b12 i/o d15 vcc j18 i/o r1 nc v8 i/o y11 i/o b13 i/o d16 i/o j19 i/o r2 i/o v9 i/o y12 i/o b14 i/o d17 vss j20 gclk / i r3 i/o v10 i/o y13 i/o b15 i/o d18 i/o k1 i/o r4 vcc v11 i/o y14 i/o b16 i/o d19 i/o k2 i/o r17 vcc v12 vccio y15 i/o b17 nc d20 i/o k3 i/o r18 i/o v13 i/o y16 i/o b18 stm e1 nc k4 vcc r19 i/o v14 i/o y17 i/o b19 nc e2 i/o k17 i r20 i/o v15 i/o y18 i/o b20 i/o e3 i/o k18 aclk / i t1 nc v16 i/o y19 i/o c1 i/o e4 i/o k19 i t2 i/o v17 i/o y20 nc c2 i/o e17 i/o k20 nc t3 i/o v18 i/o c3 i/o e18 i/o l1 i t4 nc v19 tms ql3025-rev. a
ql3025 / ql3025r 2- 33 pin descriptions pin function description tdi test data in for jtag hold high during normal operation. connect to vcc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3v supply. vccio input voltage tolerance pin connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3v supply. gnd ground pin connect to ground. pasic 3 2 ordering information ql 3025 r - 1 pq208 c * contact quicklogic regarding availability. quicklogic pasic device pasic 3 device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = fastest blank: 3.3v 0.35 micron cmos r: 3.3v 0.35 micron cmos with embedded ram ql3025-rev. a package code pf144 = 144-pin tqfp pq208 = 208-pin pqfp pb256 = 256-pin pbga operating range c = commercial i = industrial *m = military
ql3025 / ql3025r 2- 34 absolute maximum ratings vcc voltage ???????.. -0.5 to 4.6v dc input current ?.????????.. 20 ma vccio voltage???????-0.5 to 7.0v esd pad protection ?.?????.??.. 2000v input voltage ??...? -0.5 to vccio +0.5v storage temperature??..?.?.-65 c to + 150 c latch-up immunity ??????. 200 ma lead temperature ????????..??300 c operating range symbol parameter military industrial commercial unit min max min max min max vcc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 -40 85 0 70 c tc case temperature 125 c -0 speed grade 0.42 1.92 0.46 1.85 k delay factor -1 speed grade 0.41 1.69 0.42 1.55 0.46 1.50 -2 speed grade 0.41 1.41 0.42 1.29 0.46 1.25 -3 speed grade 0.42 1.14 0.46 1.10 -4 speed grade 0.42 1.02 0.46 1.00 dc characteristics symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 m a 0.9vcc v vol output low voltage iol = 16 ma [1] 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 m a ioz 3-state output leakage current vi = vccio or gnd -10 10 m a ci input capacitance [2] 10 pf ios output short circuit current [3] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [4] vi, vio = vccio or gnd 0.50 (typ) 2 ma iccio d.c. supply current on vccio 0 100 m a notes: [1] applies only to -1/-2/-3/-4 commercial grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. [2] capacitance is sample tested only. clock pins are 12 pf maximum. [3] only one output at a time. duration should not exceed 30 seco nds. [4] for -1/-2/-3/-4 commercial grade devices only. maximum icc is 3 ma for -0 commercial grade and all industrial grade devices, and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer engineering. ql3025-rev. a
ql3025 / ql3025r 2- 35 ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the ?operating range? section by the following numbers.) logic cells input-only cells symbol parameter propagation delays (ns) fanout [5] 1 2 3 4 8 12 24 tin high drive input delay 2.5 2.6 2.6 2.7 3.5 4.6 5.8 tini high drive input, inverting delay 2.6 2.7 2.7 2.8 3.6 4.7 5.9 tisu input register set-up time 4.8 4.8 4.8 4.8 4.8 4.8 4.8 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.9 1.0 1.0 1.1 1.9 3.0 4.2 tlrst input register reset delay 0.8 0.9 0.9 1.0 1.8 2.9 4.1 tlesu input register clock enable set-up time 4.1 4.1 4.1 4.1 4.1 4.1 4.1 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [6] these limits are derived from a representativ e selection of the slowest paths through the pasic 3 logic cell including typical net delays . worst case delay values for specific paths should be determined from timing analysis of your particular design. symbol parameter propagation delays (ns) fanout [5] 1 2 3 4 8 tpd combinatorial delay [6] 1.4 1.7 2.0 2.3 3.5 tsu setup time [6] 1.8 1.8 1.8 1.8 1.8 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.8 1.1 1.4 1.7 2.9 tcwhi clock high time 1.6 1.6 1.6 1.6 1.6 tcwlo clock low time 1.6 1.6 1.6 1.6 1.6 tset set delay 1.4 1.7 2.0 2.3 3.5 treset reset delay 1.2 1.5 1.8 2.1 3.3 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 pasic 3 2 ql3025-rev. a
ql3025 / ql3025r 2- 36 clock cells symbol parameter propagation delays (ns) loads per half column [7] 1 2 3 4 8 10 12 15 tack array clock delay 2.2 2.2 2.3 2.4 2.5 2.6 2.7 tgckp global clock pin delay 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 tgckb global clock buffer delay 1.5 1.6 1.6 1.7 1.8 1.9 2.0 2.1 i/o cells symbol parameter propagation delays (ns) fanout [5] 1 2 3 4 8 10 ti/o input delay (bidirectional pad) 1.8 2.1 2.4 2.7 3.9 4.6 tisu input register set-up time 4.8 4.8 4.8 4.8 4.8 4.8 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.8 1.1 1.4 1.7 2.9 3.6 tlorst input register reset delay 0.7 1.0 1.3 1.6 2.8 3.5 tlesu input register clock enable set-up time 4.1 4.1 4.1 4.1 4.1 4.1 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.6 3.0 3.6 4.1 5.2 touthl output delay high to low 2.8 3.3 3.9 4.5 5.7 tpzh output delay tri-state to high 2.1 2.6 3.1 3.7 4.8 tpzl output delay tri-state to low 2.6 3.3 4.1 4.9 6.5 tphz output delay high to tri-state [8] 2.9 tplz output delay low to tri-state [8] 3.3 notes: [7] the array distributed networks consist of 56 half columns and the global distributed networks consist of 60 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 12 loads per half column. the global clock has up to 15 loads per half column. [8] the following l oads are used for tpxz: 5 pf 1k w 5 pf 1k w tphz tplz
|
